The present invention relates to a parallel processor system, and more particularly to a parallel processor system for performing, at a high speed, a synchronous processing and the processing of deciding the end of data transmission/receipt among a plurality of processors, memories and the like.
Recently, there has been attempted that a plurality of relatively small-scale processors are caused to execute large scale computation at a higher speed than a single high-speed processor. Such a computer is generally referred to as a parallel processor system. In the case where problems are solved by means of the parallel processor system, it is necessary to exchange data among processors and synchronize processors. Accordingly, it is important that data exchange and synchronous processings are performed at a high speed in order to obtain a high-performance parallel processor system.
In each processor of the parallel processor system, generally, an execution phase and a data transfer phase alternately appear. The execution phase executes operation. The data transfer phase transfers data between the processors. For example, such a state has been described on and after page 30, IEEE MICRO magazine Vol. 10, No. 2 (April 1990). As shown in FIG. 9, in the case where a partial differential equation 50 is solved by means of a computer, calculation is repeated until an integral of the partial differential equation 50 converges in a processing 51. In the processing 51, an arithmetic processing 52 and a data transmit/receive processing 53 are alternately repeated. In the arithmetic processing 52, each processor forming the computer independently performs operation. In the data transmit/receive processing 53, data is transmitted and received between the processors. The data transmit/receive processing 53 is executed by the processor in the procedure shown in a processing 54. More specifically, a predetermined number of data are transmitted to a network by which the processors are connected to one another. The same number of data are received from the network. At this time, synchronization is carried out to check whether the processor precisely receives the predetermined number of data. If the synchronization is not correct, the data transmit/receive processing is executed again. The state of a synchronous processing will be described with reference to FIG. 10.
FIG. 10 is a block diagram showing a parallel processor system according to the prior art. In FIG. 10, the reference numerals 2a, 2b, 2c and 2d denote processing devices of the parallel processor system. Each of the processing devices 2a to 2d includes a processor 4 and a router 5. The router 5 is connected to a network 1. The parallel processor system comprises a synchronizer 12 for synchronizing the processors 4 of the processing devices 2a to 2d. The synchronizer 12 is connected to the processors 4 of the processing devices 2a to 2d.
In the conventional parallel processor system shown in FIG. 10, the synchronous processing of the data transmit/receive processing 53 shown in FIG. 9 is carried out in the following manner. When the data transmit/receive processing 53 is started, the processor 4 gives the router 5 a command to transmit and receive a predetermined number of data in the processing devices 2a to 2d. The router 5 counts the receive data. If the number of the receive data is a predetermined one, a receive ending flag is raised in the router 5. The processor 4 intermittently observes whether the receive ending flag is raised. When the receive ending flag is ascertained, the processor 4 transmits a synchronous request signal to the synchronizer 12. The synchronizer 12 observes the synchronous request signals transmitted from the processing devices 2a to 2d. When all the synchronous request signals transmitted from the processing devices 2a to 2d become complete, the synchronizer 12 transmits synchronous signals to the processing devices 2a to 2d. In response to the synchronous signals, the processing devices 2a to 2d simultaneously control the next processing.
In the conventional parallel processor system mentioned above, however, it is necessary for the processors 4 of the processing devices 2a to 2d to generate and transmit data, and intermittently observe whether the receive ending flag is raised in the router 5. For this reason, it is necessary for the processor 4 to use a part of arithmetic control capabilities thereof. Accordingly, the burden of the processor 4 is increased so that an arithmetic processing speed is lowered. It is necessary for the router 5 to count the number of the receive data so as to ascertain that the processing of receiving the receive data is completed. Consequently, the router 5 should have a complicated hardware configuration. In a processing in which the number of receive data to be received by the routers 5 of the processing devices 2a to 2d is determined depending on the state of processing execution, it is necessary for the router 5 to receive a predetermined number of receive data plural times under the detailed control of the processor 4 at the time of processing execution. In the above-mentioned parallel processor system, furthermore, it is required that the synchronizer 12 is provided so as to detect that all the data transmit/receive processings of the processing devices 2a to 2d are completed and to return the same to the processing devices 2a to 2d.